An important consideration in the packaging of integrated circuits is the efficient delivery of power and ground feeds to the semiconductor die of the integrated circuit. One method for the delivery of power to the integrated circuit involves lead frame over Chip (LOC) packaging, in which a metal lead frame rests on top of the semiconductor die. The metal lead frames employed in LOC packaging often include two metal power buses, one power bus at a positive voltage potential and the other at a ground voltage potential. Each bus or metal lead runs lengthwise along the top of the semiconductor die. The power buses provide a means by which the bond wires can be easily coupled between the power buses and the bond pads, which bond pads often lie in the center top surface of the semiconductor die. In a typical configuration, there may be half a dozen or more connections made between the bond pads of the semiconductor die and the power buses.
One drawback of LOC packaging for delivering power to the die is the capacitive effects created by the combination of the metal lead frame and the semiconductor die. In the configuration described, both the semiconductor die and the metal lead frame behave as capacitor plates, producing capacitive effects on the signals being output from the semiconductor die. The signals being transferred to and from the semiconductor die often have to switch between potential levels, and the capacitive effects produced by the combination of the semiconductor die and the lead frame tend to inhibit the fast switching between voltage potentials because of the damping effects experienced during the transition between voltage levels.
To compensate for capacitive effects created by the combination of the semiconductor die and the metal lead frame, integrated circuit designers have designed chips in which the signals that are most sensitive to parasitic capacitance, such as high frequency output signals in memory chips, and the bond pads for these signals have been moved to the four corners of the semiconductor die. In this manner, the output signals leaving the semiconductor die from the four corners of the chip are between the metal lead frame and the semiconductor die--the two plates producing capacitive effects--for only a very short distance, thereby reducing the capacitive loading on the signals that are most sensitive to parasitic capacitance. An additional benefit of placing the output signals on the four corners of the semiconductor die is a reduction in the distance that the signal must travel on the bond wires and on the lead frame before reaching the outside of the integrated circuit packaging.
If bond pads and output signals are placed on the outside corners of the semiconductor die, however, dedicated output drivers ordinarily must be placed adjacent the bond pads to drive the output signals. These output drivers, however, often require massive and dedicated power and ground feeds.